FlexRay is a communication protocol developed by a consortium of automotive manufacturers and semiconductor companies to provide a distributed control and communication system for automotive applications.
FlexRay systems comprise a plurality of buffers, wherein these buffers are configured as double buffers. Double buffers are prone to blocking which limit their use for storing and transmitting data from real-time applications. Solutions to this limitation are constantly being sought.
United States Patent Application US2004208181 describes a network computer system in which the computers transmit messages over virtual circuits established thereamong, wherein the messages are transmitted in a round-robin scheduling arrangement. However, US2004208181 does not describe the dedicated bus systems of the FlexRay protocol. Furthermore, US2004208181 does not describe the transmission of data from real-time applications. Similarly, US2004208181 does not describe the discarding of obsolete frames.
US Patent Application US20050091427 describes an integrated circuit device having a send/receive macro for serially transferring addresses and data to or from an external device via a serial transfer bus. In this case, the host CPU interrupt load is decreased by implementing a block which controls data transmission and monitors the data transmission status. This block has its own FIFO buffer where it stores data provided by the host CPU. The host is interrupted only if data transmission was not acknowledged. However, in contrast with the present invention, the invention described in US20050091427 utilizes FIFO therefore no transmission done event is sent to the host, but only FIFO is empty interrupt or the data is not acknowledged.
US Patent Application US20050157709 describes a multi-queue single-FIFO scheme for quality of service oriented communication. In this case, the host CPU interrupt load is reduced by implementing an arbiter which maintains data transmission operations on the physical medium from the connected Multi-queue single-FIFO. However, in contrast with the present invention, the invention described in US20050157709 relates to an architecture based on a FIFO. In particular, it does not relate to the double buffers of the present invention.
Similarly, “Programming ST10X167/ST10F168 CAN interrupt drivers” Application Note, 1998 STMicroelectronics, discusses host CPU programming approaches utilizing single buffers for transmission which has combined event and state interrupts for transmit buffers in a CAN communication system. However, this document does not relate to FIFO systems or double buffers.